By Francis C. Wang
Fresh technological advances have created a checking out obstacle within the electronics industry--smaller, extra hugely built-in digital circuits and new packaging suggestions make it more and more tough to bodily entry try nodes. New checking out tools are wanted for the following iteration of digital gear and loads of emphasis is being put on the advance of those tools. a few of the options now changing into renowned comprise layout for testability (DFT), integrated self-test (BIST), and automated attempt vector new release (ATVG). This e-book will offer a pragmatic creation to those and different checking out thoughts. for every strategy brought, the writer presents real-world examples so the reader can in attaining a operating wisdom of ways to settle on and observe those more and more very important trying out tools.
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Additional info for Digital Circuit Testing. A Guide to DFT and Other Techniques
Therefore we have generated a test vector (A = 0, B = 0, and C = 1). Note that the path sensitization step is called line justification and the assignment of the primary input values is called consistency operation, as defined in the D-algorithm. In the D-algorithm, there are two basic operations proposed to search for a test vector to test each fault. These two operations are defined below. D Operation: The process to select a single path or multiple paths such that the sensitized value at the fault site can be driven forward until it reaches any primary output to be detected.
L. Bearson, Analyzing errors with the Boolean difference, IEEE Transactions on Electronic Computers EC-17, July 1966. 13. Akers, S. , Universal test sets for logic networks, Proceedings of Switching and Automata Theory Symposium, October 1972. 14. Roth, J. , Diagnosis of automata failures: a calculus and a method, IBM Journal of Research and Development 10, July 1966. 15. " Krieger, Melbourne, Florida, 1974. 16. , An implicit enumeration algorithm to generate tests for combinational circuits, IEEE Transactions on Computers C-30, March 1981.
Both can generate tests to detect faults if such tests actually exist. However, PODEM is more efficient in terms of computer time used to generate the test vectors. It also uses some simple heuristics to improve its capability. Therefore, PODEM is considered a better test generation technique for complex combinational circuits. References 1. " Prentice-Hall, Englewood Cliffs, New Jersey, 1984. 2. " Scott, Foresman and Company, Glenview, Illinois, 1988. 3. " Addison-Wesley, Reading, Massachusetts, 1985.
Digital Circuit Testing. A Guide to DFT and Other Techniques by Francis C. Wang