By Weixia Xu, Liquan Xiao, Jinwen Li, Chengyi Zhang, Zhenzhen Zhu
This booklet constitutes the refereed court cases of the 20 th CCF convention on laptop Engineering and expertise, NCCET 2016, held in Xi'an, China, in August 2016. The 21 complete papers awarded have been conscientiously reviewed and chosen from a hundred and twenty submissions. they're geared up in topical sections on processor structure; software particular processors; laptop software and software program optimization; expertise at the horizon.
Read or Download Computer Engineering and Technology: 20th CCF Conference, NCCET 2016, Xi'an, China, August 10-12, 2016, Revised Selected Papers PDF
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Additional resources for Computer Engineering and Technology: 20th CCF Conference, NCCET 2016, Xi'an, China, August 10-12, 2016, Revised Selected Papers
Table 2. 854 Conclusion In order to explore the performance of digital signal processor SDR-DSP, this paper designs and implements LEVCS, a Language-Extension-based Vectorizing Compiling Scheme for SDR-DSP. This design provides a vectorized programming method with a new C-extending programming language named SDR-DSP C. The corresponding vecto‐ rizing compiler is developed for SDR-DSP, including the support for SDR-DSP C and ﬂexible data reorganization. The result of experiment shows that we can implement vectorizationon SDR-DSP correctly and can get good speedups by using LEVCS.
Benchmarks. In: Performance Evaluation and Benchmarking. CRC Press, pp. 27–44 (2006) 14. : Computer Architecture: A Quantitative Approach, 3rd edn. cn 2 National Key Laboratory of Parallel and Distributed Processing, National University of Defense Technology, Changsha 410073, People’s Republic of China Abstract. Spin-transfer torque random access memory (STT-RAM) is one of the most promising substitutes for universal main memory and cache due to its excellent scalability, high density and low leakage power.
With the same power threshold set, different utilization threshold conﬁgurations result in different energy saving. According to the test results in Fig. 9, we set the lower limit of the ﬁrst threshold value is 40%, the upper limit is 65%, and the upper and lower limit of the second threshold value are 85% and 20% respectively. The power thresholds at different PLL frequencies are 16 W, 12 W and 0 W. With this conﬁguration, the total energy consumption of parsec can be reduced by nearly 10%. 48 C.
Computer Engineering and Technology: 20th CCF Conference, NCCET 2016, Xi'an, China, August 10-12, 2016, Revised Selected Papers by Weixia Xu, Liquan Xiao, Jinwen Li, Chengyi Zhang, Zhenzhen Zhu