By Sanjay Dabral
The 1st accomplished advisor to ESD safeguard and I/O designBasic ESD and I/O layout is the 1st e-book dedicated to ESD (electrostatic discharge) security and input/output layout. Addressing the starting to be call for in for high-speed I/O designs, it bridges the space among ESD examine and present VLSI layout practices and offers a much-needed reference for practising engineers who're often referred to as upon to profit the topic at the job.This quantity offers an built-in therapy of ESD, I/O, and strategy parameter interactions that either I/O designers and technique designers can use. It examines key elements in I/O and ESD layout and checking out, and is helping the reader examine ESD and reliability concerns up entrance while making I/O offerings. Emphasizing readability and straightforwardness, this ebook makes a speciality of layout ideas that may be utilized generally as this dynamic box maintains to conform.
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Extra info for Basic ESD and I/O Design
This breakdown raises the local substrate potential sufficiently to forward bias the source and help initiate the breakdown of the TFO. Once the TFO turns on, it carries the brunt of the ESD current. Since the grounded-gate NMOS is not capable of carrying large currents, the resistor has to be chosen such that the NMOS safe current is never exceeded. This scheme worked well when the diffusions were not silicided. Silieidation has reduced its performance dramatically, primarily due to nonuniform distribution of current in the thick-field device during clamping.
The CMOS process utilizes a well to provide the bulk for the complementary transistor. This well fonnulation may also have an effect on the diodes, which is discussed next. 1. Cascaded Diodes In N-well CMOS technology a diode is actually a PNP transistor. This is illustrated in Figure 2-19, which shows a chain of four serially connected diodes. This parasitic nature provides the diode some interesting properties that can be beneficial as well as detrimental. The single-transistor element is shown in Figure 2·20.
These are deliberately drawn capacitors in addition to the parasitic capacitance already existing. At the initial stage of an ESD pulse, enough charge is coupled into the resistor such that it weakly turns on the NMOS device. By allowing the gate to tum on weakly, the snapback voltage is lowered, shown in Figure 2-13 as (VI;' It'd. If the snapback voltage is lowered sufficiently (VIl < Vd, then other fingers in an NMOS device will also snap back before anyone finger goes into a second breakdown.
Basic ESD and I/O Design by Sanjay Dabral